Title :
A 0.13 μm Low-power Race-free Programmable Logic Array
Author :
Samson, Giby ; Clark, Lawrence T.
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ
Abstract :
A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V
Keywords :
logic gates; low-power electronics; nanoelectronics; programmable logic arrays; 0.13 micron; 1.5 V; 905 MHz; AND logic; NAND gates; NOR gates; OR logic; Si; low power race-free programmable logic array; low standby power process; CMOS logic circuits; CMOS process; Circuit testing; Clocks; Delay; Logic circuits; Logic testing; Programmable logic arrays; Robustness; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320899
