VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel

Author

Zhong, Hao ; Zhang, Tong ; Haratsch, Erich F.

Author_Institution

Dept. of Electron. Comput. & Sci. Eng., Rensselaer Polytech. Inst., Troy, NY

fYear

2006

Firstpage

325

Lastpage

328

Abstract

By implementing an FPGA-based simulator, this paper investigates the semi-random construction of high-rate regular QC-LDPC codes with low error floor for the magnetic recording channel. Then a new QC-LDPC decoder hardware architecture is proposed. Finally, a read channel signal processing datapath consisting of a parallel Max-Log-MAP detector and the proposed QC-LDPC decoder is implemented in 0.13 mum CMOS. This design achieves a throughput up to 1.8Gbps under 16 iterations of LDPC decoding

Keywords

CMOS digital integrated circuits; VLSI; channel coding; magnetic recording; parity check codes; 0.13 micron; CMOS; FPGA-based simulator; VLSI design; high-rate LPDC codes; magnetic recording channel; parallel Max-Log-MAP detector; quasicyclic LDPC codes; read channel signal processing; CMOS process; Detectors; Floors; Hardware; Iterative decoding; Magnetic recording; Parity check codes; Signal processing; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320902

Filename

4114970

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1678634