IO Clock Network Skew & Performance Analysis: A Pentium-D Case Study

Accurate estimation of skew on I/O clocks is extremely critical when the part is expected to operate at a fixed frequency and any failure results in yield loss. Also, factors such as slow silicon, power saving modes, thermal throttling modes makes the data-path running on I/O clocks more critical as no timing relaxation is possible. The circuits on core clocks, on the other hand, can be binned to a lower frequency using bus ratios for slower silicon and benefit from frequency reduction during power saving modes. Further, since the I/O clock distribution typically utilizes a balanced tree structure due to its sparse usage, it suffers from higher skew compared to global clock with a tiled topology. This makes it imperative that the I/O clock performance methodology take into account all the various factors that can impact clock skew as well as slowdown in the associated datapath circuits. This paper presents a systematic skew estimation and a scientific method for performance analysis of I/O clock network. A case study on how this was adopted for Pentium-D (65 nm process) I/O clocks is presented. Key components considered are clock topology, device & interconnect in-die variation, temperature and voltage supply variation