Title :
Yield and Cost Modeling for 3D Chip Stack Technologies
Author :
Mercier, P. ; Singh, S.R. ; Iniewski, K. ; Moore, B. ; O´Shea, P.
Author_Institution :
Dept. of ECE, Alberta Univ., Edmonton, Alta.
Abstract :
It has been shown that stacking a set of known good dice into a 3D chip array may be beneficial in terms of system performance and footprint area. This paper demonstrates that, in the general sense, it is also beneficial to arrange chips into a 3D stack from yield and cost perspectives. It is shown that an optimal point occurs where cost is minimized by stacking an appropriate amount of dice into a single system
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit yield; 3D chip stack technologies; cost modeling; yield modeling; Bonding; CMOS process; Cost function; Integrated circuit interconnections; Packaging; Production systems; Routing; Stacking; System-on-a-chip; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320948
