Title :
Evolution of an effective DFT/ATG solution for sequential ASICs
Author_Institution :
HHB Syst., Inc., Mahwah, NJ, USA
Abstract :
The author traces the evolution of a sequential circuit automatic test generator. He discusses a method for user control of the automation and shows how this leads to an elegant solution to automating design for testability. Results are presented for using the resulting system, Intelligen, for several benchmark circuits. After 11 iterations, 98% coverage was achieved. This is about the same coverage achieved previously using full scan, but Intelligen provided a savings of about 11% of the die area compared to a full scan
Keywords :
application specific integrated circuits; automatic testing; integrated logic circuits; sequential circuits; Intelligen; automatic test generator; benchmark circuits; coverage; design for testability; die area; full scan; sequential ASICs; sequential circuit; user control; Application specific integrated circuits; Automatic control; Automatic testing; Circuit faults; Circuit testing; Design for testability; Integrated circuit testing; Sequential analysis; Sequential circuits; System testing;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100752
