DocumentCode :
1679533
Title :
Fastpath: a path-delay test generator for standard scan designs
Author :
Underwood, Bill ; Law, Wai-on ; Kang, Sungho ; Konuk, Haluk
Author_Institution :
Semicond. Syst. Design Technol., Motorola Inc., USA
fYear :
34608
Firstpage :
154
Lastpage :
163
Abstract :
Fastpath generates non-robust, robust or single-path-sensitization hazard-free robust path-delay tests for standard scan designs including high-impedance elements and functionally-described blocks. Results show effective and memory-efficient operation
Keywords :
automatic test equipment; automatic testing; boundary scan testing; logic testing; Fastpath; input constraints; logic algebra; memory-efficient operation; nonrobust operation; path delay test; path-delay test generator; robust operation; single-path-sensitization; standard scan designs; Circuit faults; Circuit testing; Clocks; Delay effects; Electrical fault detection; Robustness; Semiconductor device testing; System testing; Timing; Vehicle dynamics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-2103-0
Type :
conf
DOI :
10.1109/TEST.1994.527946
Filename :
527946
Link To Document :
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