Title :
A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications
Author :
Cho, Young-Jae ; Sa, Doo-Hwan ; Kim, Yong-Woo ; Lee, Kyung-Hoon ; Choi, Hee-Cheol ; Lee, Seung-Hoon ; Jeon, Young-Deuk ; Lee, Seung-Chul ; Kwon, Jong-Kee
Author_Institution :
Dept. of Electron. Eng., Sogang Univ., Seoul
Abstract :
A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital video broadcasting; low-power electronics; multimedia communication; 0.13 micron; 1.2 V; 10 bit; 2.4 mW; 4.8 mW; CMOS technology; analog-digital converters; digital multimedia broadcasting; digital video broadcasting; switched-bias power-reduction; CMOS digital integrated circuits; Clocks; Digital multimedia broadcasting; Digital video broadcasting; Energy consumption; Pipelines; Power dissipation; Sampling methods; Switching circuits; System-on-a-chip;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320892
