Title :
Die Stacking Technology for Terabit Chip-to-Chip Communications
Author :
Rahman, Arifur ; Trezza, John ; New, Bernie ; Trimberger, Steve
Author_Institution :
Xilinx Res. Labs, San Jose, CA
Abstract :
In this paper a die stacking technology, leveraging on through die via (TDV) integration and wafer bonding, is presented. Using state-of-the-art volume manufacturing environment, 10:1 aspect ratio TDV and wafer-level bonding technology are developed and initial electrical and reliability characterization results of TDVs are provided. The opportunities for die-stacking technology to alleviate chip-to-chip communication bottleneck are discussed and visions for stacked-die applications, utilizing a programmable virtual backplane, are presented
Keywords :
integrated circuit interconnections; wafer bonding; die stacking technology; electrical characterization; programmable virtual backplane; reliability characterization; state-of-the-art volume manufacturing; terabit chip-to-chip communications; through die via integration; wafer bonding; Backplanes; Bandwidth; Electronics packaging; Integrated circuit technology; Manufacturing; Semiconductor device packaging; Silicon; Stacking; Transistors; Wafer bonding;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320826
