Underfill Flow Void Solutions Through Process and Materials Interaction

Author

Kang Ji Wang ; Balachandran, R. ; Wagiman, A.N.R.

Author_Institution

Intel Technol. Sdn Bhd., Malaysia

Volume

4

Issue

12

fYear

2014

fDate

Dec. 2014

Firstpage

1999

Lastpage

2003

Abstract

Silicon dies were thinned down and bump pitch became smaller to have a lot of input/output in electronic device packages especially in package on package configuration. This presents challenges on underfill (UF) dispense processing. UF voids occurred near the dispense side of bumps in multiple dispense pass technology. In this paper, we will review UF flow behavior on thin die technology, as well as the process and material interaction that cause UF void formation. Process optimization, such as the time between two dispense passes has become a critical parameter to eliminate UF voids without causing UF epoxy roll up that can cause reliability failure.

Keywords

flip-chip devices; optimisation; semiconductor device packaging; semiconductor device reliability; UF flow behavior; bump pitch; electronic device packages; materials interaction; multiple dispense pass technology; thin die technology; thinned down; underfill dispense processing; underfill flow void solutions through process; Computational fluid dynamics; Flip-chip devices; Silicon; Substrates; Surface tension; Viscosity; Flip chip; UF roll up; UF voids; package on package; underfill (UF); underfill (UF).;

fLanguage

English

Journal_Title

Components, Packaging and Manufacturing Technology, IEEE Transactions on

Publisher

ieee

ISSN

2156-3950

Type

jour

DOI

10.1109/TCPMT.2014.2363014

Filename

6939629