DocumentCode
1680249
Title
A 1.6Gbps Digital Clock and Data Recovery Circuit
Author
Hanumolu, Pavan Kumar ; Kim, Min Gyu ; Wei, Gu-Yeon ; Moon, Un-Ku
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
fYear
2006
Firstpage
603
Lastpage
606
Abstract
A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop filter to the voltage controlled oscillator and achieves low jitter performance. Test chip fabricated in a 0.13mum CMOS process achieves BER < 10-12 , plusmn1500ppm lock-in range, plusmn2500ppm tracking range, recovered clock jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6Gbps
Keywords
CMOS digital integrated circuits; analogue-digital conversion; clocks; jitter; 0.13 micron; 1.2 V; 1.6 Gbit/s; 12 mW; CMOS process; digital clock and data recovery circuit; digital loop filter; digital-to-analog converters; low jitter performance; voltage controlled oscillator; Bandwidth; Circuits; Clocks; Digital filters; Frequency locked loops; Jitter; Moon; Virtual colonoscopy; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location
San Jose, CA
Print_ISBN
1-4244-0075-9
Electronic_ISBN
1-4244-0076-7
Type
conf
DOI
10.1109/CICC.2006.320829
Filename
4115031
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