• DocumentCode
    1681166
  • Title

    A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery

  • Author

    Oh, Tae-Young ; Yi, Seung-Hyun ; Yang, Sung-Hyun ; Lim, Byong-Chan ; Hong, Kuk-Tae

  • Author_Institution
    LG Electron.
  • fYear
    2006
  • Firstpage
    745
  • Lastpage
    748
  • Abstract
    This paper presents a digital PLL for low long-term jitter clock recovery. A jitter reduction scheme for digitally controlled oscillator is proposed and 39% jitter reduction is observed. A 5-phase digital phase frequency detector (PFD) has 265 ps resolution and controls output clock phase by 132 ps step. The long-term jitter is measured as 460 ps pk-pk. This digital PLL is implemented in 0.18 mum CMOS process using 0.417 mm2 and consumes 61.0 mW power
  • Keywords
    CMOS integrated circuits; digital phase locked loops; synchronisation; timing jitter; 0.18 micron; 61.0 mW; CMOS process; digital phase frequency detector; digital phased lock loops; digitally controlled oscillator; jitter reduction scheme; low long-term jitter clock recovery; Adders; Circuits; Clocks; Delay; Digital control; Digital filters; Jitter; Oscillators; Phase frequency detector; Phase locked loops;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    1-4244-0075-9
  • Electronic_ISBN
    1-4244-0076-7
  • Type

    conf

  • DOI
    10.1109/CICC.2006.320966
  • Filename
    4115061
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1681166