A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder

Author

Sait, Sadiq M. ; Damati, Ali F. ; Rahman, Mushfigur

Author_Institution

King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

fYear

1989

Firstpage

307

Lastpage

310

Abstract

A novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived paths and provide the decoded output. The systolic algorithm is modeled in AHPL to verify functional correctness. Implementation details are discussed. It is found that the proposed systolic design compares favorably with previous implementations of Viterbi decoders in terms of speed and modularity

Keywords

VLSI; cellular arrays; circuit CAD; decoding; AHPL; VLSI design; Viterbi decoder; Viterbi decoding; branch metric computation; error correction codes; survived branches; systolic algorithm; systolic architecture; Algorithm design and analysis; Circuits; Computer architecture; Convolutional codes; Hardware; Maximum likelihood decoding; Petroleum; Systolic arrays; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean

Conference_Location

Lisbon

Type

conf

DOI

10.1109/MELCON.1989.50043

Filename

50043