A systolic array for neural network implementation

Author

Pazienti, Francesco

Author_Institution

ALCATEL Face Res. Centre, Pomezia, Italy

fYear

1991

Firstpage

981

Abstract

The implementation of a multilayer perceptron, based on a linear array of interconnected processing elements (PEs), is described. An iterative formulation of the network model is presented and the mapping with the computing architecture is derived. A preliminary version of the proposed algorithm has been implemented on the APx Accelerator, a parallel processor system using a proprietary VLSI (the ACIIM chip). The efficiency of the approach is considered for real-time systems, where the general-purpose programming model allows the APx to run the neural model and other processing tasks required by the application

Keywords

VLSI; neural nets; systolic arrays; ACIIM chip; APx Accelerator; computing architecture; interconnected processing elements; iterative formulation; linear array; multilayer perceptron; neural model; neural network; parallel processor system; programming model; proprietary VLSI; real-time systems; systolic array; Computer architecture; Computer networks; Iterative algorithms; Multi-layer neural network; Multilayer perceptrons; Neural networks; Neurons; Signal processing algorithms; Systolic arrays; Transmission line matrix methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 1991. Proceedings., 6th Mediterranean

Conference_Location

LJubljana

Print_ISBN

0-87942-655-1

Type

conf

DOI

10.1109/MELCON.1991.162006

Filename

162006