Title :
Statistical and Corner Modeling of Interconnect Resistance and Capacitance
Author_Institution :
Syst. & Technol. Group, IBM Semicond. R&D Center, Essex Junction, VT
Abstract :
We describe an innovative and comprehensive interconnect Spice model for IBM 65 nm technology. The model links the variability in the model to the variations in BEOL litho, deposition, etch, and polish process steps, which is an industry first. It provides correct Monte Carlo simulation results, offers correct corner modeling capability, and can also generates a set of optimal interconnect corner models instantly without running Monte Carlo simulations, which is another industry first
Keywords :
Monte Carlo methods; SPICE; integrated circuit interconnections; integrated circuit modelling; statistical analysis; 65 nm; Monte Carlo simulation; deposition process steps; etch process steps; interconnect Spice model; interconnect capacitance; interconnect resistance; litho process steps; optimal interconnect corner models; polish process steps; statistical model; Circuit optimization; Circuit simulation; Delay; Integrated circuit interconnections; Parasitic capacitance; Predictive models; Routing; Semiconductor device modeling; Semiconductor process modeling; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320845
