On-line testable decimation filter design for AMS systems

Author

Naal, M.A. ; Simeu, E. ; Mir, S.

Author_Institution

TIMA Lab., Grenoble, France

fYear

2003

Firstpage

83

Lastpage

88

Abstract

This paper presents an implementation of on-line testing techniques for the case of a decimation filter. The decimation filter is used in a ΣΔ analogue-to-digital converter that is in turn used in a built-in-self-test (BIST) circuitry for mixed-signal core testing. Thus, the filter itself must be self-testable. Three different one-line self-test techniques are studied and compared for a 0.18 μm CMOS technology. The first one uses a non-concurrent structural test technique and the others are both based on semi-concurrent test methodologies. In all cases, the on-line test circuitry is automatically synthesized and exploits the idle time of the functional units to apply either a structural or a functional test.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; built-in self test; design for testability; filters; sigma-delta modulation; ΣΔ analogue-to-digital converter; 5.668 MHz; AMS systems; CMOS technology; built-in-self-test circuitry; design-for-test technique; functional test; high-level synthesis for testability; idle time; mixed-signal core testing; non-concurrent structural test; on-line testable decimation filter design; on-line testing techniques; one-line self-test techniques; register-transfer level; self-testable filter; semi-concurrent test; Automatic testing; Built-in self-test; CMOS technology; Circuit synthesis; Circuit testing; Filters; Flow graphs; High level synthesis; Redundancy; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE

Print_ISBN

0-7695-1968-7

Type

conf

DOI

10.1109/OLT.2003.1214371

Filename

1214371