DocumentCode
1681991
Title
An efficient BIST scheme for high-speed adders
Author
Nikolos, D.G. ; Nikolos, D. ; Vergos, H.T. ; Efstathiou, C.
Author_Institution
Comput. Eng. & Informatics Dept., Partas Univ., Patras, Greece
fYear
2003
Firstpage
89
Lastpage
93
Abstract
In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal performance penalty, small hardware overhead and the benefits of at-speed testing.
Keywords
adders; built-in self test; feedback; high-speed integrated circuits; LFSR; MISR; at-speed testing; built-in self-test; fault coverage; hardware overhead; high-speed adders; high-speed circuits; integrated circuits; partially inverted feedback; performance penalty; pseudorandom BIST scheme; response compactor; single stuck-at fault model; test pattern generator; test sequence length; test set size; Adders; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Hardware; Informatics; Integrated circuit testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Print_ISBN
0-7695-1968-7
Type
conf
DOI
10.1109/OLT.2003.1214372
Filename
1214372
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