• DocumentCode
    1682
  • Title

    UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

  • Author

    Xiaowen Wu ; Yaoyao Ye ; Jiang Xu ; Wei Zhang ; Weichen Liu ; Nikdast, Mahdi ; Xuan Wang

  • Author_Institution
    Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. of Technol., Hong Kong, China
  • Volume
    22
  • Issue
    5
  • fYear
    2014
  • fDate
    May-14
  • Firstpage
    1082
  • Lastpage
    1095
  • Abstract
    As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processing cores. Traditionally, to maximize design flexibility, interchip and intrachip communication architectures are separately designed under different constraints. Jointly designing communication architectures for both interchip and intrachip communication could, however, potentially yield better solutions. In this paper, we present a unified inter/intrachip optical network, called UNION, for chip multiprocessors (CMPs). UNION is based on recent progresses in nanophotonic technologies. It connects not only cores on a single CMP, but also multiple CMPs in a system. UNION employs a hierarchical optical network to separate interchip communication traffic from intrachip communication traffic. It fully utilizes a single optical network to transmit both payload and control packets. The network controller on each CMP not only manages intrachip communications, but also collaborates with each other to facilitate interchip communications. We compared UNION with a matched electrical counterpart in 45-nm process. Simulation results for eight real CMP applications show that on average UNION improves CMP performance by 3× while reducing 88% of network energy consumption.
  • Keywords
    integrated optoelectronics; multiprocessing systems; nanophotonics; network-on-chip; optical fibre networks; optical interconnections; telecommunication traffic; CMPs; UNION; chip multiprocessors; control packets; hierarchical optical network; interchip communication architectures; interchip communication traffic; intrachip communication architectures; nanophotonic technology; network controller; network energy consumption; optical NoC; processing cores; size 45 nm; unified inter-intrachip optical network; Chip multiprocessor (CMP); interchip optical network; optical NoC; photonic interconnects; photonic interconnects.;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2013.2263397
  • Filename
    6544298