Title :
Analyzing SEU effects is SRAM-based FPGAsb
Author :
Violante, M. ; Ceschia, M. ; Reorda, M. Sonza ; Paccagnella, A. ; Bernardi, P. ; Rebaudengo, M. ; Bortolato, D. ; Bellato, M. ; Zambolin, P. ; Candelori, A.
Author_Institution :
Politecnico di Torino, Italy
Abstract :
Commercial-off-the-shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory. The method combines radiation testing for technology characterization and simulation-based fault injection for SEU propagation. Experimental results we gathered with the purpose of modeling the effects of SEUs in the FPGA configuration memory are reported and commented.
Keywords :
SRAM chips; fault simulation; fault tolerance; field programmable gate arrays; integrated circuit testing; radiation hardening (electronics); FPGA configuration memory; SEU effects; SEU propagation; SRAM-based FPGA devices; dependability; fault tolerant systems; radiation testing; simulation-based fault injection; single event upsets; technology characterization; CMOS technology; Costs; Face detection; Fault detection; Fault tolerant systems; Field programmable gate arrays; Prototypes; Silicon; Single event upset; Testing;
Conference_Titel :
On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Print_ISBN :
0-7695-1968-7
DOI :
10.1109/OLT.2003.1214377
