Fast Reliability Analysis Method for Sequential Logic Circuits

Reliability analysis of combinational logic circuits using error probabilities methods, such as PTM, has been widely developed and used in literature. However, using these methods for reliability analysis of sequential logic circuits will lead to inaccurate results, because of existence of loops in their architecture. In this paper a new method is proposed based on converting the sequential circuit to a secondary combinational circuit and applying an iterative reliability analysis to the resulting configuration. Experimental results demonstrate good accuracy levels for this method.