DocumentCode
1682505
Title
Analysis of bit transition count for EDAC encoded FSM
Author
Venkateswaran, N. ; Balaji, V. ; Mahalingam, V. ; Rajaprabhu, T.L.
Author_Institution
Waran Res. Found., Chennai, India
fYear
2003
Firstpage
166
Abstract
The focus of this paper is to present a bit transition count analysis for various error detection and correction (EDAC) schemes through a detailed simulation. The simulation also brings out the impact of various EDAC schemes - linear, BCH, m-out-of-n, Berger and SEC-MUED - on bit transition count with respect to number of FSM partitions under different partitioning objective functions for low power. A decrease up to 30 percent in bit transitions count under the three partitioning objectives has been observed.
Keywords
error correction; error detection; fault tolerance; finite state machines; BCH codes; Berger codes; EDAC encoded FSM; FSM partition; SEC-MUED codes; WARF FSM power analyzer; WARFFPA tool; bit transition count analysis; error detection and correction; finite state machine; linear codes; m-out-of-n codes; partitioning objective function; Analytical models; Educational institutions; Encoding; Error analysis; Error correction; Error correction codes; Fault detection; Fault tolerance; Hamming distance; Linear code;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Print_ISBN
0-7695-1968-7
Type
conf
DOI
10.1109/OLT.2003.1214391
Filename
1214391
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