Title :
Design Methodology of On-Chip Power Distribution Network
Author :
Tohya, Hirokazu ; Toya, Noritaka
Author_Institution :
ICAST Inc., Tokyo
Abstract :
The effect of the capacitors in the power distribution network (PDN) was reviewed based on electromagnetic theory. It was clarified that the capacitors used in the PDN are not suitable for high-frequency decoupling or for lowering the impedance. Based on this result, a novel design methodology of an on-chip PDN is proposed in this paper. The low-impedance lossy line (LILL) technology is used as the PDN instead of capacitors and other components. This methodology improves both the performance of the SoC and also the signal transmission rate markedly because the LILL in the PDN shortens the rise time of the signal. An analysis of the effect of the novel design methodology, SPICE simulation result, and an example of an on-chip LILL structure for the SoC are presented in this paper
Keywords :
SPICE; computer power supplies; power aware computing; system-on-chip; SPICE simulation; SoC; electromagnetic theory; low-impedance lossy line technology; on-chip power distribution network; signal transmission; Capacitors; Delay estimation; Design methodology; Dielectric losses; Frequency; Impedance; Inverters; Network-on-a-chip; Power systems; Switches;
Conference_Titel :
Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on
Conference_Location :
Richardson, TX
Print_ISBN :
1-4244-0670-6
Electronic_ISBN :
1-4244-0670-6
DOI :
10.1109/DCAS.2006.321038
