Design and Implementation of a Video Compression Technique for High Definition Videos Implemented on a FPGA

High definition videos contain huge data to be transmitted and received, which is difficult to be sent and stored. In this paper a compression technique based on binary motion vector technique is used to compress HD videos. In which the process of searching for the best matching block for each current block occurs. The proposed technique keeps HD quality with at least Peak Signal to Noise Ratio 62 dB and along with 26% compression ratio on gray scale. The proposed technique is implemented on a Xilinx Vertex 2 2V250fg456 FPGA. The maximum operating speed of the hardware is 63.8 MHz. The FPGA utilization is 12.37% of total CLB slices and 8.61% of total latches.