DocumentCode
1682555
Title
Evaluation of the quality of testing path delay faults under restricted input assumption
Author
Krasniewski, Andrzej
Author_Institution
Inst. of Telecommun., Warsaw Univ. of Technol., Poland
fYear
2003
Firstpage
168
Lastpage
170
Abstract
We show that in the case when the set of vector pairs that occur at the input of a combinatorial network in the system environment is restricted (as it is for most applications), the information on such restrictions should be accounted for when evaluating the quality of testing delay faults, especially if the test sequence "mimics" the normal operation, i.e. if only those vector pairs that may occur in normal operation are applied during testing.
Keywords
circuit CAD; delays; fault simulation; integrated circuit testing; Boolean function; combinatorial network; path delay faults testing; system environment; test sequence; vector pairs; Boolean functions; Circuit faults; Circuit testing; Crosstalk; Field programmable gate arrays; Integrated circuit noise; Logic devices; Propagation delay; System testing; Working environment noise;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Print_ISBN
0-7695-1968-7
Type
conf
DOI
10.1109/OLT.2003.1214393
Filename
1214393
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