• DocumentCode
    1682563
  • Title

    A chip-level process for power switching module integration and packaging

  • Author

    Liang, Zhenxian ; van Wyk, J.D. ; Lee, Fred C.

  • Author_Institution
    Center for Power Electron. Syst., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • Volume
    3
  • fYear
    2004
  • Firstpage
    1932
  • Abstract
    A process module, incorporating embedding of multiple power semiconductor chips in a flat ceramic frame and planar metallization interconnect technologies, has been developed to fabricate active power chip scale packages (CSP), multichip modules (MCMs), and integrated power electronics modules (IPEMs). This integrated chips technology features structure compactness and process integrity, compared to other multilevel packaging methods. Thus, power switching module, including controller and driver, sensor and filter, and power switches can be manufactured with a planar integration technology and packaged in 3-D form. An example IPEM, incorporating power factor correction (PFC) and DC/DC switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized. The electrical performance improvement, which includes reduction in parasitics and increase in efficiency, has been demonstrated. Furthermore, a highly functional integrated PFC switching module with embedded capacitor, current sensor and doubled side cooling has been fabricated in an integrated planar process scheme. The obtained experimental results are presented with prototypes.
  • Keywords
    DC-DC power convertors; ceramic packaging; chip scale packaging; cooling; embedded systems; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; multichip modules; power factor correction; power integrated circuits; power semiconductor switches; thermal management (packaging); 3-D packaging; CSP; DC-DC switching; MCM; PFC; capacitor; chip-level process; current sensor; distributed power system; doubled side cooling; flat ceramic frame; front-end converter application; integrated chips technology; integrated planar process module; integrated power electronics modules; multichip modules; multiple power semiconductor chips; planar integration technology; planar metallization interconnect technology; power chip scale packages; power factor correction; power switching module integration; power switching module packaging; Ceramics; Chip scale packaging; Driver circuits; Electronics packaging; Metallization; Multichip modules; Power electronics; Power semiconductor switches; Semiconductor device packaging; Sensor phenomena and characterization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industry Applications Conference, 2004. 39th IAS Annual Meeting. Conference Record of the 2004 IEEE
  • ISSN
    0197-2618
  • Print_ISBN
    0-7803-8486-5
  • Type

    conf

  • DOI
    10.1109/IAS.2004.1348733
  • Filename
    1348733