Title :
A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA
Author :
Jyo, T. ; Kuroda, Tadahiro ; Ishikuro, Hiroki
Author_Institution :
Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan
Abstract :
This paper presents a small size, low-power inductive-coupling receiver for wireless proximity communication. Area efficient active inductor peaking is used to expand the bandwidth of low voltage LNA. Proposed LNA can operate intermittently, synchronized with received pulse timing and reduces the power consumption at low data rate. Clock is extracted from the received pulse signal by simple combination of imbalanced inverters. The fabricated test chip in 65nm-CMOS occupies 0.035mm2 and achieved 1.6Gbps with power consumption of 1.76mW at 0.8V power supply.
Keywords :
CMOS analogue integrated circuits; clock and data recovery circuits; inductors; low noise amplifiers; low-power electronics; pulse circuits; radio receivers; CMOS process; area efficient active inductor peaking; bit rate 1.6 Gbit/s; fabricated test chip; intermittently operating LNA; low data rate; low voltage LNA; power 1.76 mW; power consumption; power supply; pulse extracting clock recovery circuit; received pulse signal; received pulse timing; size 65 nm; small size low-power inductive-coupling receiver; voltage 0.8 V; wireless proximity communication; Active inductors; CMOS integrated circuits; Clocks; Power demand; Receivers; Transceivers; Wireless communication; Low Noise Amplifier; inductive-coupling; intermittent operation; proximity communication;
Conference_Titel :
Radio and Wireless Symposium (RWS), 2013 IEEE
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-2929-3
Electronic_ISBN :
2164-2958
DOI :
10.1109/RWS.2013.6486693