Title :
A comparative study of design for testability methods using high-level and gate-level descriptions
Author :
Chickermane, V. ; Lee, J. ; Patel, J.H.
Author_Institution :
Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
A comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits is presented. Based on the examination of the results DFT techniques that use high-level circuit information are proposed. The results obtained after partial scan selection by a high-level DFT tool are compared with results obtained by a gate-level partial scan tool. This detailed comparative study demonstrates that a DFT tool can make a more effective selection of partial scan flip-flops by exploiting the high-level circuit information, and by accurately predicting the hard-to-test areas of a circuit.<>
Keywords :
design for testability; logic testing; benchmarking; design for testability methods; gate-level descriptions; gate-level partial scan tool; gate-level test generator; high-level descriptions; high-level test generator; partial scan flip-flops; Design for testability; Logic circuit testing;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279302
