• DocumentCode
    1683519
  • Title

    Valid clocking in wavepipelined circuits

  • Author

    Lam, W.K.C. ; Brayton, R.K. ; Sagiovanni-Vincentelli

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1992
  • Firstpage
    518
  • Lastpage
    525
  • Abstract
    An analysis of valid clock rates in wavepipelined circuits using a technique called timed Boolean functions is presented. It is shown that the valid intervals for the clock period can be disconnected. Thus, it is insufficient to known only the minimum valid clock period in guaranteeing proper operation of pipelined circuits. Analytic expressions for the valid clock intervals in terms of both topological delay and two-vector longest and shortest delays are provided. Also uncertainties arising from manufacturing are taken into account. Some potential difficulties in computing the exact valid clock intervals are illustrated by demonstrating discontinuity and nonmonotonicity of the harmonic number H( tau ) (the number of valid simultaneous data waves allowed) as a function of the clock period tau .<>
  • Keywords
    circuit CAD; clocks; timing circuits; clocking; minimum valid clock period; pipelined circuits; shortest delays; timed Boolean functions; topological delay; two vector longest delays; wavepipelined circuits; Clocks; Design automation; Timing circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-3010-8
  • Type

    conf

  • DOI
    10.1109/ICCAD.1992.279318
  • Filename
    279318