Assignment of global memory elements for multi-process VHDL specifications

A method for the synthesis of the global memory structure for a behavioral VHDL specification which consists of several concurrent processes is described. The global memory cells may be implemented as separate registers or RAMs. Emphasis was laid on the minimization of both the area demand and timing demand due to access conflicts. The VHDL description is modeled as a Petri net. The cases of this Petri net are regarded as possible states of the system. The conflicts are then estimated on the basis of the probabilities that the system is in a certain state. Finally the global signals are combined to larger memory structures by a clustering algorithm which is guided by both a decrease in area cost and possible conflicts.<>