Title :
A logic simulation engine based on a modified data flow architecture
Author :
Mahmood, A. ; Baker, W.I. ; Herath, J. ; Jayasumana, A.
Author_Institution :
Washington State Univ., Richland, WA, USA
Abstract :
An optimum application-specific data flow architecture for accelerating the standard event driven logic simulation is developed. A conservative distributed simulation algorithm which minimizes the use of NULL messages is also developed, along with a pseudodynamic data flow architecture to implement this distributed algorithm efficiently. A comparison of the standard event driven algorithm-based data flow accelerator to the distributed simulation algorithm-based accelerator is made on several benchmark circuits. The distributed simulation algorithm on the specialized data flow accelerator outperforms the standard event driven algorithm based data flow accelerator by a factor of three in most cases.<>
Keywords :
circuit analysis computing; discrete event simulation; distributed algorithms; logic CAD; parallel architectures; NULL messages; algorithm-based accelerator; benchmark circuits; conservative distributed simulation algorithm; event driven logic simulation; logic simulation engine; modified data flow architecture; Circuit simulation; Design automation; Discrete event simulation; Distributed algorithms; Parallel architectures;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279343
