DocumentCode :
1684478
Title :
A helper thread based EDP reduction scheme for adapting application execution in CMPs
Author :
Ding, Yang ; Kandemir, Mahmut ; Raghavan, Padma ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
fYear :
2008
Firstpage :
1
Lastpage :
14
Abstract :
In parallel to the changes in both the architecture domain - the move toward chip multiprocessors (CMPs) - and the application domain - the move toward increasingly data-intensive workloads - issues such as performance, energy efficiency and CPU availability are becoming increasingly critical. The CPU availability can change dynamically due to several reasons such as thermal overload, increase in transient errors, or operating system scheduling. An important question in this context is how to adapt, in a CMP, the execution of a given application to CPU availability change at runtime. Our paper studies this problem, targeting the energy-delay product (EDP) as the main metric to optimize. We first discuss that, in adapting the application execution to the varying CPU availability, one needs to consider the number of CPUs to use, the number of application threads to accommodate and the voltage/frequency levels to employ (if the CMP has this capability). We then propose to use helper threads to adapt the application execution to CPU availability change in general with the goal of minimizing the EDP. The helper thread runs parallel to the application execution threads and tries to determine the ideal number of CPUs, threads and voltage/frequency levels to employ at any given point in execution. We illustrate this idea using two applications (Fast Fourier Transform and MultiGrid) under different execution scenarios. The results collected through our experiments are very promising and indicate that significant EDP reductions are possible using helper threads. For example, we achieved up to 66.3% and 83.3% savings in EDP when adjusting all the parameters properly in applications FFT and MG, respectively.
Keywords :
fast Fourier transforms; grid computing; microprocessor chips; multi-threading; processor scheduling; CMP; CPU availability; EDP reduction scheme; MultiGrid; chip multiprocessors; data-intensive workloads; energy-delay product; fast Fourier transform; helper threads; operating system scheduling; thermal overload; Application software; Availability; Computer architecture; Computer science; Energy consumption; Energy efficiency; Frequency; Runtime; Voltage; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
Conference_Location :
Miami, FL
ISSN :
1530-2075
Print_ISBN :
978-1-4244-1693-6
Electronic_ISBN :
1530-2075
Type :
conf
DOI :
10.1109/IPDPS.2008.4536297
Filename :
4536297
Link To Document :
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