A probabilistic timing approach to hot-carrier effect estimation

An approach for estimating hot-carrier induced degradation in MOS transistor circuits is presented. The approach uses probabilistic timing simulation techniques to estimate the cumulative effects of all possible inputs on hot-carrier effect (HCE) degradation in each transistor in the circuit in a single run rather than using exhaustive or Monte Carlo simulations. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.<>