DocumentCode :
1685063
Title :
HIMALAYAS-A hierarchical compaction system with a minimized constraint set
Author :
Lee, J.-F. ; Tang, D.T.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
1992
Firstpage :
150
Lastpage :
157
Abstract :
A hierarchical compactor, HIMALAYAS (HIerarchical MAcro LAYout ASsembler), developed for constructing big macro layouts, is discussed. The hierarchical compaction problem is formulated as an integer linear programming (ILP) problem. Two algorithms are presented to reduce the problem size, in order to make the ILP approach practical. The first algorithm reduces the number of variables to a small set of pitch variables, while the second algorithm reduces the number of equations by restricting the constraint generation within a small set of regions, called the minimum cover. These reductions bring in considerable saving in computation time for layouts with cell repetitions or cell alignments. As a result, the ILP method can be used to solve the compaction problem for very big macros. Experimental results for MCNC benchmark examples are also given.<>
Keywords :
circuit layout CAD; hierarchical systems; integer programming; linear programming; macros; microassembling; modules; HIMALAYAS; Hierarchical Macro Layout Assembler; MCNC benchmark examples; cell alignments; cell repetitions; computation time; constraint generation; hierarchical compaction system; high density module assembly; integer linear programming; minimized constraint set; minimum cover; pitch variables; problem size reduction; Design automation; Hierarchical systems; Integer programming; Linear programming; Microassembly;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
Type :
conf
DOI :
10.1109/ICCAD.1992.279384
Filename :
279384
Link To Document :
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