A 6-bit 800MS/s flash ADC in 0.35μm CMOS

Author

Ghasemzadeh, Mehdi ; Soltani, Arefeh ; Akbari, Amin ; Hadidi, Khayrollah

Author_Institution

Microelectron. Res. Lab., Urmia Univ., Urmia, Iran

fYear

2015

Firstpage

234

Lastpage

238

Abstract

In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. An optimized resistance ratio averaging scheme is applied to: (1) reduce the offset, nonlinearity, (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors. The proposed ADC is simulated by Hspice using 0.35 μm TSMC technology and shows 32.24 dB/45.9 dB SNDR/SFDR, 5.06 bits ENOB, and the low power consumption of 45.12 mW from a 3.3V supply.

Keywords

CMOS digital integrated circuits; MOSFET; analogue-digital conversion; circuit optimisation; integrated circuit modelling; low-power electronics; power consumption; CMOS; ENOB; Hspice; NMOS transistors; SFDR; SNDR; TSMC technology; flash ADC; flash analog-to-digital converter; mismatch insensitivity; optimized resistance ratio averaging scheme; power 45.12 mW; power consumption; size 0.35 mum; voltage 3.3 V; Analog-digital conversion; Ash; CMOS integrated circuits; CMOS technology; Logic gates; Preamplifiers; Solid state circuits; Averaging technique; Entirely NMOS; Flash ADC; Low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits & Systems (MIXDES), 2015 22nd International Conference

Conference_Location

Torun

Print_ISBN

978-8-3635-7806-0

Type

conf

DOI

10.1109/MIXDES.2015.7208517

Filename

7208517