Analysis and two proposed design methodologies for optimizing power efficiency of a class D amplifier output stage

Author

Tan, M.T. ; Chang, J.S. ; Cheng, Z.H. ; Tong, Y.C.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

Volume

1

fYear

1998

Firstpage

281

Abstract

In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of a Class D output stage realized using the finger and waffle layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency: (i) optimization to a single modulation index point, and (ii) optimization to a range of modulation indices. For the design of an output stage with optimum power efficiency (and small IC area), we recommend the waffle layout realization optimized to a range of modulation indices. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs

Keywords

circuit optimisation; integrated circuit layout; power amplifiers; IC area; aspect ratio; class D amplifier; computer simulation; design; finger layout; modulation index; optimization; output stage; power dissipation; power efficiency; transistor; waffle layout; Contact resistance; Design methodology; Design optimization; Fingers; High power amplifiers; Inverters; Parasitic capacitance; Power dissipation; Pulse width modulation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.704416

Filename

704416