An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Presents a polynomial time technology mapping algorithm, called Flow-Map, that optimally solves the lookup-table (LUT)-based field-programmable gate array (FPGA) technology mapping problem for depth minimization for general Boolean networks. This theoretical breakthrough makes a sharp contrast with the fact that the conventional technology mapping problem in library-based designs is NP-hard. A key step in Flow-Map is to compute a minimum height K-feasible cut in a network, solved by network flow computation. The algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several postprocessing operations. The Flow-Map algorithm was tested on a a set of benchmarks and achieved reductions of both the network depth and the number of LUTs in mapping solutions as compared with previous algorithms.<>