Title :
Graph algorithms for clock schedule optimization
Author :
Shenoy, N. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.L.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
For performance-driven synthesis of sequential circuits, the optimal clocking problem is considered, and it is shown that it is reducible to a parametric shortest path problem. Constraints are used that take into account both the short and long paths. The main contributions are efficient graph algorithms to solve the set of constraints necessary for correct clocking.<>
Keywords :
circuit CAD; clocks; graph theory; optimisation; scheduling; sequential circuits; clock schedule optimization; constraints; graph algorithms; level sensitive latches; optimal clocking problem; parametric shortest path problem; performance-driven synthesis; sequential circuits; Clocks; Design automation; Graph theory; Optimization methods; Scheduling; Sequential logic circuits;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279401
