DocumentCode :
1685499
Title :
Configuration of boundary scan chain for optimal testing of clusters of non boundary scan devices
Author :
Choi, Y.-H. ; Jung, T.
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
fYear :
1992
Firstpage :
13
Lastpage :
16
Abstract :
Testing of boards containing a mixture of boundary scan components and clusters of non-boundary scan devices is considered. If a tester cannot contact the non-scan circuitry, the inputs and outputs of onboard boundary scan devices may be used as virtual tester pins. In this case, the time for testing the clusters depends on how the boundary scan chips are connected into a longer scan chain. A technique for configuring a chain of boundary scan chips to minimize the test time for clusters is presented.<>
Keywords :
circuit CAD; design for testability; printed circuit design; printed circuit testing; boundary scan chips; boundary-scan chain configuration; design for testability; nonboundary scan device clusters; optimal testing; printed circuit board testing; test time minimization; virtual tester pins; Design automation; Design for testability; Printed circuit layout; Printed circuit testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
Type :
conf
DOI :
10.1109/ICCAD.1992.279406
Filename :
279406
Link To Document :
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