Title :
Configuring multiple scan chains for minimum test time
Author :
Narayanan, S. ; Gupta, R. ; Breuer, M.
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angels, CA, USA
Abstract :
The high test time for serial scan designs can be reduced by the use of multiple scan chains. The problem of optimally constructing multiple scan chains so as to minimize the overall test time is considered. Rather than following the traditional practice of using equal length chains, the chains are allowed to be of different lengths; this can lead to lower test times. The main idea of this approach is to assign those scan elements that are more frequently accessed to shorter scan chains. Given a design with N scan elements, and given that k scan chains are to be used for applying tests, an algorithm of complexity O(kN/sup 2/) is presented for configuring the chains such that the overall test application time is minimized. By analyzing a range of circuit topologies, test time reductions as large as 40% over equal length chain configurations are demonstrated.<>
Keywords :
computational complexity; design for testability; integrated circuit testing; logic CAD; logic testing; minimisation; network topology; algorithm complexity; chain lengths; circuit topologies; design for testability; minimum test time; multiple scan chain configuration; scan elements; serial scan designs; Circuit topology; Complexity theory; Design automation; Design for testability; Integrated circuit testing; Logic circuit testing; Minimization methods;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279408
