DocumentCode
1685744
Title
Architectural tradeoffs in field-programmable-device-based computing systems
Author
Chan, Pak K. ; Schlag, Martine D F
Author_Institution
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
fYear
1993
Firstpage
152
Lastpage
161
Abstract
Reprogrammable Field-Programmable Gate Arrays (FPGAs) have enabled the realization of high-performance and affordable reconfigurable computing engines. The authors examine the architectural tradeoffs involved in designing general purpose FPGA-based computing systems with field-programmable gate arrays and field-programmable interconnects. The fact that FPGAs provide both programmable logic and programmable interconnects raises numerous design issues that need to be considered with care. Factors that influence the tradeoffs are routability, rearrangeability and speed
Keywords
logic arrays; reconfigurable architectures; IQ160; Xilinx XC4010; architectural tradeoffs; field-programmable gate arrays; field-programmable interconnects; field-programmable-device-based computing systems; folded Clos network; rearrangeability; rearrangeable Clos switching networks; reconfigurable computing engines; routability; speed; Buildings; Computer architecture; Delay; Field programmable gate arrays; High performance computing; Logic design; Programmable logic arrays; Programmable logic devices; Routing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
FPGAs for Custom Computing Machines, 1993. Proceedings. IEEE Workshop on
Conference_Location
Napa, CA
Print_ISBN
0-8186-3890-7
Type
conf
DOI
10.1109/FPGA.1993.279468
Filename
279468
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