DocumentCode :
1685775
Title :
IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology
Author :
Derlecki, Mariusz ; Borejko, Tomasz ; Pleskacz, Witold A.
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
fYear :
2015
Firstpage :
334
Lastpage :
338
Abstract :
This paper presents a sixth-order IF polyphase band-pass filter design in 28 nm FD-SOI technology. This filter has been synthesized from a low-pass Butterworth filter prototype. The filter´s bandwidth is 1.2 MHz and its center frequency is 2 MHz. A calibration technique using back-gate biasing that is available in fully depleted SOI to minimize the mismatch impact, has been also described. The two filters have been designed using two different types of transistors (regular P/NMOS and flip-well P/NMOS). The power consumption is 1.4 mW. The simulation results of the designed filter have also been presented in this paper.
Keywords :
Butterworth filters; band-pass filters; calibration; low-pass filters; silicon-on-insulator; FD-SOI technology; IF polyphase filter design; P/NMOS; back-gate biasing; bandwidth 1.2 MHz; calibration technique; frequency 2 MHz; low-pass Butterworth filter prototype; power 1.4 mW; sixth-order IF polyphase band-pass filter; size 28 nm; transistors; 28 nm FD-SOI; Gm-C structure; Polyphase filter; back-gate biasing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Mixed Design of Integrated Circuits & Systems (MIXDES), 2015 22nd International Conference
Conference_Location :
Torun
Print_ISBN :
978-8-3635-7806-0
Type :
conf
DOI :
10.1109/MIXDES.2015.7208538
Filename :
7208538
Link To Document :
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