Title :
Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications
Author :
Halauko, Aleh ; Borejko, Tomasz ; Pleskacz, Witold A.
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
Abstract :
In this paper a comparison of four low noise amplifiers (LNAs), designed in fully depleted SOI 28 nm technology, has been presented. The objective of the presented work was to verify the usability of all kinds of MOSFET transistors that are available in UTBB for RF analog designs. The inductively degenerated cascodes were used in simulations. Such topology achieves high gain and low noise figure (NF). Simulated amplifiers were designed for a high sensitivity GNSS receiver, which operates in the Galileo/GPS E1/L1 band. The implemented circuits demonstrate the gain of 22.3 dB and the consumption current of 2.5 mA, with NF equal to 1.92 dB. For all amplifiers the supply voltage is 0.6 V and the silicon die estimated area is equal to 0.7 mm2.
Keywords :
MOSFET; integrated circuit design; low noise amplifiers; low-power electronics; radio receivers; radiofrequency integrated circuits; silicon-on-insulator; FD-SOI technology; GNSS receiver; Galileo/GPS E1/L1 band; MOSFET transistors; RF analog designs; UTBB; current 2.5 mA; fully depleted SOI technology; gain 22.3 dB; low noise amplifiers; low noise figure; low voltage LNA; size 28 nm; ultra-thin body and box; voltage 0.6 V; CMOS integrated circuits; Gain; Global Positioning System; Impedance; Impedance matching; MOSFET; CMOS; FDSOI; GNSS; GPS; Galileo; IoT; LNA; NF; RF; RFIC; UTBB; back-gate; wearables;
Conference_Titel :
Mixed Design of Integrated Circuits & Systems (MIXDES), 2015 22nd International Conference
Conference_Location :
Torun
Print_ISBN :
978-8-3635-7806-0
DOI :
10.1109/MIXDES.2015.7208542
