A field programmable accelerator for compiled-code applications

Author

Lewis, David M. ; Van Ierssel, Marcus H. ; Wong, Daniel H.

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont., Canada

fYear

1993

Firstpage

60

Lastpage

67

Abstract

The paper describes a special purpose application accelerator using field programmable gate arrays to accelerate a range of applications. The accelerator is designed to support applications by allowing the user to implement a processor with an instruction set designed for the specific application being accelerated, using specialized instructions to implement critical fragments of the application. A compiled-code software organization is used to reduce overhead operations. A prototype has been built, and the first application to be ported to it, logic simulation, is underway

Keywords

instruction sets; logic CAD; logic arrays; program compilers; reconfigurable architectures; R-3000 code; Xilinx 4005; compiled-code software organization; field programmable accelerator; field programmable gate arrays; instruction set; logic simulation; special purpose application accelerator; specialized instructions; Acceleration; Circuit simulation; Data structures; Delay; Hardware; Logic gates; Logic testing; Performance evaluation; Runtime; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1993. Proceedings. IEEE Workshop on

Conference_Location

Napa, CA

Print_ISBN

0-8186-3890-7

Type

conf

DOI

10.1109/FPGA.1993.279478

Filename

279478