DocumentCode
1685973
Title
Memory model effects on application performance for a lightweight multithreaded architecture
Author
Li, Sheng ; Kuntz, Shannon ; Kogge, Peter ; Brockman, Jay
Author_Institution
Dept. of Electr. Eng., Univ. of Notre Dame, Notre Dame, IN
fYear
2008
Firstpage
1
Lastpage
8
Abstract
In this paper, we evaluate the effects of a partitioned global address space (PGAS) versus aflat, randomized distributed global address space (DGAS) in the context of a lightweight multithreaded parallel architecture. We also execute the benchmarks on the Cray MTA-2, a multithreaded architecture with a DGAS mapping. Key results demonstrate that distributing data under the PGAS mapping increases locality, effectively reducing the memory latency and the number of threads needed to achieve a given level of performance. In contrast, the DGAS mapping provides a simpler programming model by eliminating the need to distribute data and, assuming sufficient application parallelism, can achieve similar performance by leveraging large numbers of threads to hide the longer latencies.
Keywords
parallel architectures; distributed global address space; lightweight multithreaded architecture; partitioned global address space; Bandwidth; Computer languages; Context modeling; Counting circuits; Delay; Dissolved gas analysis; Electronics packaging; Multithreading; Parallel processing; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
Conference_Location
Miami, FL
ISSN
1530-2075
Print_ISBN
978-1-4244-1693-6
Electronic_ISBN
1530-2075
Type
conf
DOI
10.1109/IPDPS.2008.4536356
Filename
4536356
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