Optimization of capacitive divider for 8-bit DAC realized in 65 nm CMOS process

Capacitor based DACs are common designer´s choice for projects realized in nanometer technologies. Designs kits provide several devices that can be used as capacitors. However, they exhibit serious differences in terms of linearity, minimum area and sensitivity to process disturbances The paper presents analysis of capacitive divider design to be used in 8-bit DAC realized in 65 nm CMOS process. Various devices utilized as capacitor are examined in order to select the most suitable one for the DAC implementation in respect to resolution, conversion time and layout area.