Testing high speed DRAMs

If test of high speed DRAMs poses a new challenge for test engineers and test makers, then it would seem that the Rambus DRAMs, which have the fastest pin bandwidth of any DRAM in the world, would present the greatest challenge of all. However, at Rambus we have devised a test strategy that minimizes added test cost by allowing our devices to co-exist with the standard manufacturing flow of conventional pagemode devices. Two features have been added to the DRAM logic to facilitate our test strategy. First, a special test mode is incorporated into the Rambus interface that allows direct access to the core from the device pins. This mode provides a simple RAS/CAS-like access mechanism that can be used by existing equipment to exercise the core. Second, a PLL bypass mechanism is incorporated that allows the protocol logic to be functionally tested at low speed. These features allow the device to be tested with conventional low and medium speed memory testers. The only change to the test flow comes at final test