DocumentCode
1686606
Title
Testing issues on high speed synchronous DRAMs
Author
Lee, Wha-Joon
Author_Institution
Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
fYear
34608
Firstpage
363
Abstract
The test programming becomes very much complicated due to functionality and special features implemented in SDRAMs. Considering the combination of speed variations and operational modes, the number of the test items would easily exceed beyond the acceptable limit. The SDRAM testing issues are listed as follows: high speed tests with a slow production tester; load board and load circuit design for high speed testing; and test program development for the new features
Keywords
DRAM chips; automatic test software; automatic testing; fault diagnosis; peripheral interfaces; production testing; very high speed integrated circuits; CTT; GTL; LVTTL; SDRAM testing; high speed synchronous DRAM; high speed tests; interface standards; load board; load circuit design; noise; operational modes; speed variations; test programming; Circuit noise; Circuit testing; Clocks; Graphics; Microprocessors; Production; Random access memory; SDRAM; Software testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1994. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2103-0
Type
conf
DOI
10.1109/TEST.1994.527973
Filename
527973
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