Title :
Aliasing-free signature analysis for RAM BIST
Author :
Yarmolik, V.N. ; Nicolaidis, M. ; Kebichi, O.
Author_Institution :
Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
Abstract :
Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, we fake advantage from the regularity of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST
Keywords :
built-in self test; fault diagnosis; logic testing; random-access storage; RAM BIST; aliasing; aliasing-free signature analysis; data compaction; effectiveness; fault coverage reduction; information loss; output response compactors; signature verification; word-oriented RAM; Analytical models; Built-in self-test; Circuit faults; Circuit testing; Compaction; Fault detection; Information analysis; Pattern analysis; Read-write memory; Test pattern generators;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527978
