• DocumentCode
    1687832
  • Title

    Interference suppression using DPLL with notch frequency characteristic

  • Author

    Inoue, Takashi ; Hikawa, Hiroomi ; Mori, Shinsaku

  • Author_Institution
    Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
  • fYear
    1989
  • Firstpage
    2084
  • Abstract
    The authors propose a new digital phase-locked loop (DPLL) with notch frequency characteristic (DPLL-N), which suppresses the low-frequency output phase fluctuation caused by interference. The loop consists of two first-order, multilevel, quantized DPLLs connected by an equivalent differentiator with two delay circuits. The system has the desired attenuation in the low-frequency band. The performance of the loop is analyzed theoretically and verified by computer simulation. It is found that the output phase fluctuation caused by the interference can be suppressed without suppressing the modulated signal
  • Keywords
    digital circuits; interference suppression; phase-locked loops; delay circuits; digital PLL; equivalent differentiator; first-order PLL; interference suppression; multilevel quantised type; notch frequency characteristic; output phase fluctuation; phase-locked loop; simulation model; Attenuation; Circuits; Computer simulation; Delay; Fluctuations; Frequency; Interference suppression; Performance analysis; Phase locked loops; Phase modulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1989., IEEE International Symposium on
  • Conference_Location
    Portland, OR
  • Type

    conf

  • DOI
    10.1109/ISCAS.1989.100785
  • Filename
    100785