Genetic Algorithms with Scalable I/O Macromodels to Find the Worst Case Corner in High-Speed Server Electrical Analysis

Performing time domain electrical analysis on high-seed high-end server systems is exhaustive in terms of simulation time consumed and CPU memory. There have been many macromodeling techniques proposed in the past to model both the active and passive components of an electrical interface. These macromodels help in reducing the simulation time and CPU memory consumption while maintaining the accuracy. A full blown design space exploration is needed to find the worst case corner(s) of an electrical interface. The number of simulations needed for this would be in the order of thousands. Performing these simulations, even with scalable I/O macromodels, is cumbersome and parsing the output data from these simulations is equally tedious. In this paper, a genetic algorithm (GA) based approach is described to find the worst case corner(s) in highspeed server electrical analysis. It has been shown that by using GA based approach the worst case corner(s) can be estimated without performing a full-blown Monte Carlo sweep. Scalable I/O macromodels are used along with GA based approach to enhance the efficiency of the proposed technique