High speed pipelined CMOS encoder for flash A/D converters

Different CMOS encoders for flash A/D (analog-to-digital) converters are compared from the speed and noise points of view. The proposed pipelined CMOS encoder gives a load capacitance to each comparator of no more than a unit inverter. The error probability of the encoder in the most significant bit is much less than that in the least significant bit. A true single-phase clock was used to achieve high speed and simple structure. A 6-bit flash A/D converter using very simple, nonlatched comparators associated with this encoder was fabricated in a 3-μm CMOS process and tested. The highest sampling rate measured was 200 megasamples/s at a power supply of ±3.5 V